Self-healing chip-to-chip interface

ABSTRACT

A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to an improved data processing system, and in particular, to a method and apparatus for routing data. Still more particularly, the present invention provides a method and apparatus for routing data between chips across a bus.

2. Description of Related Art

As computer systems become increasingly more complex, the number of interconnections between integrated circuits also increases. The number of interconnections between chips, such as microprocessors, memory, and input/output chips is increasing to numbers, such as tens of thousands of interconnections between chips in a computer system. All of these signals sent between different components pass through a chip's package or module, a board, and possibly across a connector to another board and then to another module arriving at a final destination. All of these signal paths are required to be manufactured and remain defect free to avoid the possibility of a system failure.

A service call is required when a defective component is present or a working component fails. The defective or failing component often causes part or all of the computer system to be unavailable.

Further, during testing and manufacturing of components, any components identified with defects, such as a non-functional signal path, are scrapped or discarded. Only components meeting and passing tests are used to build final shippable computer systems. Typically in large, very dense components, thousands of signal paths are present. The yields of usable components are often very low. In many cases, a yield of fifty percent is considered to be very good.

Therefore, it would be advantageous to have an improved method, apparatus, and computer instructions to handle defects or failures in signal paths between different chips.

SUMMARY OF THE INVENTION

The present invention provides a method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a diagram illustrating chips with a self-healing interface in accordance with a preferred embodiment of the present invention;

FIG. 2 is a diagram illustrating components used in dynamically routing signal paths in accordance with a preferred embodiment of the present invention;

FIG. 3 is a diagram illustrating testing components in a driver chip in accordance with a preferred embodiment of the present invention;

FIG. 4 is a diagram illustrating testing components in a receiver chip in accordance with a preferred embodiment of the present invention;

FIGS. 5A and 5B are flowcharts of a process used for testing and re-routing signal paths in accordance with a preferred embodiment of the present invention; and

FIG. 6 is a flowchart of a process for detecting bus errors during functional operation and re-routing signal paths on a bus in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

With reference now to the figures, and in particular to FIG. 1, a diagram illustrating chips with a self-healing interface is depicted in accordance with a preferred embodiment of the present invention. In this example, driver chip 100 sends signals to receiver chip 102 over bus 104. A bus is a common pathway or channel providing a connection between devices. Bus 104 provides a path for signals to travel between driver chip 100 and receiver chip 102. Additionally, spare bit line 106 also provides a connection between driver chip 100 and receiver chip 102.

The mechanism of the present invention employs routing 108 and routing 110 to manage or handle a defective signal path or a failure in a signal path within bus 104. These routing mechanisms, routing 108 and routing 110, allow for driver chip 100 and receiver chip 102 to repair themselves to allow signal paths to be dynamically reconfigured. Such a mechanism allows for defects to exist in the bus while still maintaining operation and functionality for the system. The re-routing provided by the present invention is accomplished by including spare bit line 106. A spare bit line or signal path may be added for each chip. The number of spare signal paths employed may vary depending on the particular implementation. For example, a spare signal path may be added for each bus or group of interconnections. More than one spare signal path may be added for a bus or group of interconnections. Further, the spare signal path, such as spare bit line 106, may be normally functional or nonfunctional, but is not required for complete or partial operation.

During a manufacturing test or during functional operation, if any signal path in bus 104 is detected or diagnosed to be defective, signaling is re-routed around the defective signal path by activating or switching into operation spare bit line 106.

For example, an N-bit wide bus on a send chip, such as driver chip 100, is routed to the chip's drivers and sent across any arbitrary interconnect—module, board, connector, or card to a receiver chip. If, however, a defect is detected on bit 5 for example, all of the configuration latches on bits 6 through N are re-routed using a routing mechanism, such as routing 108. In this manner, the signal paths for the bits are re-routed by steering or routing bit 5 to bit 6, bit 6 to bit 7, and bit 7 to bit 8. This routing continues through the signal paths such that the spare signal path, such as spare bit line 106, is included. Similarly on the receive side, such as at receiver chip 102, the bits are reconfigured, using a routing mechanism, such as routing 110, to route around the defective bit 5.

Normal operation can then take place with the defective signal path being successfully removed. Such a defect could exist on any of the components in the path or on any of the signals on the bus. Further, additional spare signals and steering logic may be added to increase the number of allowed defects. Other variations include, for example, a 72-bit bus that may be steered or narrowed to a 36-bit bus reducing the effective bandwidth of the bus but allowing the customer to remain operational until a service call could be scheduled.

Turning now to FIG. 2, a diagram illustrating components used in dynamically routing signal paths is depicted in accordance with a preferred embodiment of the present invention. In this example, driver chip 200 sends signals to receiver chip 202 across bus 204. Additionally, spare bit line 206 is used to allow for dynamic reconfiguration of the signal paths in the event a defective signal path is identified.

Driver chip 200 includes data source 208. Data source 208 contains various logic and integrated circuits for providing functionality. Driver chip 200 also includes driver bit logic 210, 212, 214, and 216. These logics provide testing functions that are employed to determine whether defects are present in the signal paths on bus 204 and on spare bit line 206. These components have their inputs connected to data source 208. The output of these components is connected to multiplexers 218, 220, 222, and 224. Most of the multiplexers have an input from two different driver bit logic units. Multiplexer 218 has one input connected to ground with a second input connected to driver bit logic 210. Multiplexer 220 has one input connected to driver bit logic 210 and a second input connected to driver bit logic 212. Multiplexer 222 has one input connected to driver bit logic 212 and a second input connected to driver bit logic 214. Multiplexer 224 has one input connected to driver bit logic 214 and a second input connected to driver bit logic 216.

The select or control input of these multiplexers is connected to configuration latches 226, 228, and 230. The output of multiplexers 218, 220, 222, and 224 is connected to drivers 232, 234, 236, and 238. These drivers are connected to bit lines 240, 242, and 244 in bus 204 with driver 238 being connected to spare bit line 206. In these examples, the multiplexers are 2:1 multiplexers. These multiplexers are added to provide a routing function, such as that in routing 108 in FIG. 1. The select inputs in these multiplexers are used to control or select the input into these components.

These multiplexers are programmable through configuration latches 226, 228, and 230 in these examples. In these examples, the configuration latches are illustrated as scan only latches. In normal operation and in the absence of any defects, the bus is N bits wide and all the configuration latches are set to zero.

If one of the configuration latches is set to one, such a signal changes the routing in the signal paths across bus 204.

In receiver chip 202, data destination 246 contains logic and integrated circuits for providing functions to operate and process signals received across bus 204. Receiver chip 202 also includes receiver bit logic 248, 250, 252, and 254. These components are used in testing for defects in signal paths across bus 204 and spare bit line 206. The input to these components is connected to multiplexers 256, 258, 260, and 262. As with the multiplexers in driver chip 200, the inputs selected by these multiplexers are controlled through latches, such as configuration latches 264, 266, and 268. The inputs to multiplexers 256, 258, 260, and 262 are connected to receivers 270, 272, 274, and 276.

More specifically, multiplexer 256 has one input connected to receiver 270 and a second input connected to receiver 272. Multiplexer 258 has one input connected to receiver 272 and a second input connected to receiver 274. Multiplexer 260 has one input connected to receiver 274 and a second input connected to receiver 276. Finally, multiplexer 262 has one input connected to receiver 276 and a second input connected to ground.

In these examples, four bit lines are illustrated in the bus for purposes of describing the present invention. Such an illustration is not meant as a limitation to the number of lines that may be provided for signal paths in bus 204. Of course, any number of bit lines may be employed depending on the particular implementation. Further, a single spare bit line is illustrated. Additional spare bit lines may be used depending on the particular design or desired configuration.

The configuration latches and multiplexers illustrated in driver chip 200 form the components for a routing mechanism, such as routing 108 in FIG. 1. Similarly, the configuration latches and multiplexers in receiver chip 202 form the components for a routing mechanism, such as routing 110 in FIG. 1.

In these examples, the routing function is illustrated as taking the form of multiplexers controlled by configuration latches. This mechanism is shown as being located between the driver bit logic and the drivers. The location of the mechanism within a chip may change depending on the location in which the critical timing is located. The actual location of this mechanism within the chip will depend on particular design parameters for a specific chip.

With reference now to FIG. 3, a diagram illustrating testing components in a driver chip is depicted in accordance with a preferred embodiment of the present invention. Testing system 300 is employed to detect defective or failed signal lines in a bus, such as bus 204 in FIG. 2. In this example, testing system 300 includes data shift register units 302, 304, and 306, which form a shift register for testing system 300. Testing system 300 also includes multiplexers 308, 310, and 312. These components are included in the driver bit logic units illustrated in FIG. 2. For example, data shift register unit 302 and multiplexer 308 form a driver bit logic unit, such as driver bit logic 210 in FIG. 2. The output of multiplexers 308, 310, and 312 is connected to multiplexers or other types of re-routing logic used to dynamically re-route signal paths. Multiplexers 308, 310, and 312 serve to allow the functional transmission of data, such as that from a data source, while also allowing for data, such as a test pattern, to be transmitted. The test pattern is generated by test control logic 318 in these examples.

Initially, data shift register units 302, 304, and 306, which form a shift register, are cleared to zero through reset or scanning. In this example, a wire test, commonly used for testing components, may be initiated. In a wire test, every wire or signal path is driven to a logic level zero with all of the receivers expecting a logic level zero. Then, a single signal wire or signal path is changed to a logic level one. The receiver corresponding to the driver is the only receiver expecting a logic level one. This one is then “walked” to the next signal wire in the sequence. With this test, only one wire or signal path in the system is at a logic level one at any time, while all other wires or signal paths are at a logic zero. This test enhances an ability to identify or catch “subtle” opens or shorts between lines. During such a test, a “walking one” is shifted onto the first data shift register, data shift register unit 302 by test control logic 318. This walking one may then be shifted to the next shift register unit until all of the signal paths have been tested. In a similar fashion, a “walking zero” may be employed. The one or zero signal is propagated onto the bus in response to the assertion of a signal, “WIRE_TEST”, being applied to test control logic 318. This walking pattern is shifted every 16-bit time on the bus to allow a slow checking of bus signals. This walking one is then sent to data shift register unit 304 by data shift register unit 302. The walking one may later be sent to data shift register unit 306.

Turning now to FIG. 4, a diagram illustrating testing components in a receiver chip is depicted in accordance with a preferred embodiment of the present invention. Testing system 400 is located in a receiver chip, such as receiver chip 202 in FIG. 2.

In this example, testing system 400 includes data shift register units 402, 404, and 406, which form a shift register. This testing system also includes received data/expected data comparators 408, 410, and 412. Data is received in these comparators from the data shift registers as well as from receivers 414, 416, and 418. The input of these receivers is connected to scan latches 420, 422, and 424. The output of these scan latches also is connected to receivers 426, 428,and 430. These receivers provide a path to a data destination for data signals. Scan latches 420, 422, and 424 are connected to multiplexers or other routing units used to dynamically reconfigure signal paths.

In this example, the scan latches, receivers, comparators, and data shift registers are components located in receiver hit logic units, such as those illustrated in FIG. 2. For example, scan latch 420, receiver 426, receiver 414, received data/expected data comparator 408, and data shift register unit 402 are components found in a single receiver bit logic unit, such as receiver bit logic 252 in FIG. 2. A test using these data shift registers may be initiated by test control logic 434. The test control logic may be located off the chip and provide signals to the chip on which these data shift registers are located.

Initially, these data shift registers are reset to zero through reset/scanning. Wire testing as well as random data tests may be performed using these components. In a similar fashion, a walking one or zero may be shifted into the data shift registers for comparison with signals received from the transmitting chip, such as signals generated by test system 300 in FIG. 3. In a similar fashion, data may be shifted into these shift registers for comparison.

In this manner, the testing systems illustrated in FIGS. 3 and 4 allow for the identification of defective or failed signal paths in a bus. Further, these specific examples are intended as illustrations of one implementation in which testing may be implemented. Of course, other types of testing systems or components may be employed depending on the particular design. Based on these signals, dynamic re-routing of signal paths may be initiated.

With reference now to FIGS. 5A and 5B, flowcharts of a process used for testing and re-routing signal paths are depicted in accordance with a preferred embodiment of the present invention. The process illustrated in FIGS. 5A and 5B may be implemented in a routing mechanism, such as routing 108 and routing 110 in FIG. 1. The steps illustrated in these figures may be implemented as instructions executed by a processor on the chip or in hardware. These routing functions also could be implemented in a specific routing chip separate from the chips providing the functions. The particular location of the routing function will depend on where the critical timing for the signal paths is located.

The process begins by executing a wire test between the driver bus on the driver chip and the receiver bus on the receiver chip (step 500). This test may be implemented using components, such as those illustrated in FIGS. 3 and 4 above. The receiver chip is queried to see if errors occurred during the wire test (step 502). A determination is made as to whether errors are found in the wire test (step 504). If errors are found in the wire test, the per-bit self-test error registers are scanned out from the receiver chip and a determination is made as to whether only one bit has failed per group of data lines on the bus (step 506). The grouping of data lines to a spare bit line may change depending on different implementations. Further, more than one spare bit line may be associated with a group of data lines.

Next, a determination is made as to whether more than one error is found (step 508). If more than one error is not found, the drv_reconfig and rcv_reconfig vectors needed to swap out the bad bit are determined (step 510). In step 510, the contents of the reconfiguration latches are identified. The vectors are basically the contents of the reconfiguration latches.

The vectors are scanned into both the driver and the receiver chips (step 512). The scanning of vectors into the chips is employed to re-route the signal paths to exclude the failed or defective signal path and include the spare signal path provided by a spare bit line. Informational status is posted on this error (step 514). After each self-test, a self-test pass or a self-test fail signal is passed to the control logic, such as test control logic 434 in FIG. 4. If a self-test fail is reported, the test control logic may scan/read out the contents of the error latches from the receiver. This information may be placed into reconfiguration latch data and loaded into the configuration latches in both the driver chip and the receiver chip to reconfigure the signal paths. The wire test is executed between the driver on the driver chip and the receiver bus on the receiver chip (step 516).

A determination is made as to whether additional errors are found in a second wire test (step 518). If additional errors are not found in the second wire test, a normal initialization sequence is initiated for the bus and the chip is placed into a functional mode (step 520) with the process terminating thereafter.

Returning again to step 518, if additional errors are found in the second wire test, the per-bit self-registers are scanned out from the receiver chip, the bus, the failed bits are logged, a fatal error is posted for this bus (step 522) and the process terminates thereafter. With reference again to step 508, if more than one error is found, a fatal error is posted for this bus, the failed bits are logged (step 524) and the process terminates thereafter. Turning again to step 504, if no errors are found in wire test, the process proceeds to step 520 as described above.

The testing and reconfiguration of the bus described in FIG. 5 may occur during different times, such as during manufacturing tests, during normal power on of a system, or at any time when normal bus error detection indicates a failure or failures on the bus. This normal bus error detection may include, for example, parity checking or error detection/correction coding.

Additionally, the mechanism of the present invention may be implemented within a computer system in which monitoring is performed for errors. Turning now to FIG. 6, a flowchart of a process for detecting bus errors during functional operation and re-routing the signal paths on a bus is depicted in accordance with a preferred embodiment of the present invention. The process illustrated in FIG. 6 may be implemented in a data processing system, such as, for example, a personal computer, a workstation, or a server computer. The detection performed by the process in FIG. 6 may occur during functional operation of the bus to allow repairs or reconfiguration of a failing bus. This testing may use standard error detection methods, such as error detection/correction coding (ECC).

The process begins by detecting a bus error (step 600). The bus on which the error occurred is identified (step 602). A determination is made as to whether a threshold error level has been reached for the bus (step 604). When a threshold error level is detected on the particular bus, operation or data transfers on the bus are halted (step 606). In this step, the computer enters a diagnostic mode. In this mode, testing of the bus is initiated (step 608). The testing executed in step 608 employs the steps described with respect to FIGS. 5A and 5B above.

A determination is then made as to whether operation of the computer system may continue (step 610). This step employs information returned by the testing performed on the bus to determine whether defective or failed signal paths are present and whether these defects or failures are correctable. If operation can be continued, the operation of the system resumes (step 612) with the process terminating thereafter. Otherwise, the process terminates without resuming operation of the computer system. Returning again to step 604, if the threshold for the bus has not been reached, the process terminates.

The detection of a bus error in step 600 may be implemented using a double-bit error detect/single-bit error scheme in addition to other well-known error detection schemes. With this type of error detection, a single-bit error in a bus can be detected and corrected without causing a system data integrity error, while two bits failing will indicate an error. Two failing bits result in an inability to correct the error, thus causing a system data integrity error. If, during operation, a bus experiences multiple single-bit errors, the bus may indicate a “hard” failure, such as, for example, a wire has “opened up”. If the “threshold” number of these single-bit/correctable errors has been reached on the bus, the normal bus operation can be stopped, and the bus may be tested for these “hard” fails via the previously described wire test mechanism, and the hard failure “healed” by the reconfiguration mechanism described above. Thus, if during operation, a potential hard fail is detected, (via multiple single-bit errors), that hard failure can be corrected via the self-healing bus mechanism before any potentially uncorrectable error (soft or hard) caused by two bits failing (an “uncorrectable ECC error”) occurs on the bus.

In the detection of the bus error in step 600, it also is possible, by analyzing the “syndrome” bits in the ECC mechanism, to identify the failing bit on the bus. As described above, step 600 may be implemented using well-known ECC algorithms. If multiple cases of failure of the same bit occur as detected by the threshold mechanism inferred in step 604, this situation may indicate a bus signal which, due to noise or interference or some other mechanism, is “error-prone”, a so-called “soft error”. If this soft error occurs repeatedly on the same bit, the process described in steps 510 and 512 of FIG. 5, may be employed without performing the wire test described in steps 501 and 502 to reconfigure the bus to swap out the signal line identified by the ECC mechanism.

Thus both hard errors, detected by wire test, or soft errors, detected by error detection/correction coding techniques) can be used to detect faulty signals, and the invention used to reconfigure around these failures employed.

Although ECC encoding techniques have been described as example implementations for detecting errors, any error detection method may be employed to detect hard or soft errors. Once such an error is detected and isolated to a single failing data path, the mechanism of the present invention may be used to reconfigure the bus to eliminate the faulty data path and use the spare data path.

Thus, the present invention provides an improved method, apparatus, and computer instructions for a self-healing chip-to-chip interface. The mechanism provides this interface through dynamic reconfiguration of signal paths between chips. When a defective or failed signal path is identified, the signals are re-routed to exclude the use of that signal path and include a spare signal path. The extent of re-routing that may occur depends on the number of spare signal paths provided on the chip. In addition, in some cases reduced bandwidth may be employed by reconfiguring the signal paths to send less data bits. In this manner, continued functionality or limited functionality may be provided until a chip or component can be replaced. Further, if a spare signal path is used in place of a defective one, the yield of components may increase because such a component may be considered a good or passing component, rather than a defective one.

It is important to note that while the present invention has been described in the context of a fully functioning data processing system, those of ordinary skill in the art will appreciate that the processes of the present invention are capable of being distributed in the form of a computer readable medium of instructions and a variety of forms and that the present invention applies equally regardless of the particular type of signal bearing media actually used to carry out the distribution. Examples of computer readable media include recordable-type media, such as a floppy disk, a hard disk drive, a RAM, CD-ROMs, DVD-ROMs, and transmission-type media, such as digital and analog communications links, wired or wireless communications links using transmission forms, such as, for example, radio frequency and light wave transmissions. The computer readable media may take the form of coded formats that are decoded for actual use in a particular data processing system.

The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 

1. A chip comprising: a data source; a set of drivers and a spare driver, wherein the set of drivers and the spare driver are connected to a set of switch units; wherein the set of switch units are connected to, and receive inputs from, a set of driver bit logic units, which include a spare driver bit logic unit; wherein the set of driver bit logic units are connected to and receive inputs from the data source, and wherein the set of driver bit logic units are not included in the data source; a set of bit lines and a spare bit line; wherein the set of switch units provides a connection between the set of bit lines and the set of bit logic units, and the spare bit line and the spare driver bit logic unit, and wherein the set of switch units further can reconfigure the connection to exclude a selected bit line from the set of bit lines and use the spare bit line if the selected bit line fails to carry a signal; wherein the set of driver bit logic units include corresponding shift registers and corresponding multiplexers, wherein the corresponding shift registers provide an input into the corresponding multiplexers, wherein the corresponding shift registers in the set of driver bit logic units are coupled together serially, and wherein the chip further comprises: test control logic that generates a test pattern, wherein the test control logic is coupled to only a first one of the corresponding shift registers for providing the test pattern to the first one of the corresponding shift registers.
 2. The chip according to claim 1, wherein the test pattern is shifted from the first one of the shift registers to a next one of the shift registers, and wherein the test pattern is shifted through each one of the set of driver bit logic units one at a time.
 3. A chip comprising: a data destination; a plurality of receivers comprising a set of receivers and a spare receiver, wherein the set of receivers and the spare receiver are connected to a set of switch units; wherein the set of switch units are connected to a set of receiver bit logic units, which include a spare receiver bit logic unit; wherein the set of receiver bit logic units are connected to the data destination, and further wherein the set of receiver bit logic units are not included in the plurality of receivers; a set of bit lines and a spare bit line; and wherein the set of switch units provides a connection between the set of bit lines and the set of receiver bit logic units, and the spare bit line and the spare receiver bit logic unit, and wherein the set of switch units can reconfigure the connection to exclude a selected bit line from the set of bit lines and to use the spare bit line if the selected bit line fails to carry a signal; wherein the set of receiver bit logic units include corresponding comparators and corresponding shift registers, and wherein the corresponding comparators compare a test signal that was received by the set of receiver bit logic units to an expected test pattern that is provided to the corresponding comparators by the corresponding shift registers, wherein the corresponding shift registers are coupled together serially, and wherein the chip further comprises: test control logic that generates the test pattern, wherein the test control logic is coupled to only a first one of the corresponding shift registers for providing the test pattern to the first one of the corresponding shift registers.
 4. The chip according to claim 3, wherein the test pattern is shifted from the first one of the shift registers to a next one of the shift registers, and wherein the test pattern is shifted through each one of the set of receiver bit logic units one at a time.
 5. An apparatus for managing a set of signal paths between a driver chip and a receiver chip, the apparatus comprising: a set of bit lines and a spare bit line; the driver chip including: a data source; a set of bit logic units and a spare driver bit logic unit, wherein the set of driver bit logic units and the spare driver bit logic unit are connected to the data source; a set of switch units, wherein the set of switch units provides a connection between the set of bit lines and the set of driver bit logic units, and the spare bit line and the spare driver bit logic unit, and wherein the set of switch units can reconfigure the connection to exclude a selected bit line from the set of bit lines and to use the spare bit line if the selected bit line fails to carry a signal, wherein the connection includes a set of drivers connecting the set of switches to the set of bit lines; and wherein the set of driver bit logic units includes corresponding shift registers and corresponding multiplexers, and wherein the corresponding shift registers provide an input into the corresponding multiplexers; and the receiver chip including: a data destination; a plurality of receiver bit logic units comprising a set of receiver bit logic units and a spare receiver bit logic unit, wherein the set of receiver bit logic units and the spare receiver bit logic unit are connected to the data destination; a set of switch units, wherein the set of switch units provides a connection between the set of bit lines and the set of receiver bit logic units, and the spare bit line and the spare receiver bit logic unit, and wherein the set of switch units can reconfigure the connection to exclude a selected bit line from the set of bit lines and to use the spare bit line if the selected bit line fails to carry a signal, wherein the connection includes a set of receivers connecting the set of switches to the set of bit lines; and wherein the set of receiver bit logic units includes corresponding comparators and corresponding shift registers, and wherein the corresponding comparators compare a test signal that was received by the chip to an expected test pattern that is provided to the corresponding comparators by the corresponding shift registers.
 6. The apparatus according to claim 5, wherein the input provided by the corresponding shift registers into the corresponding multiplexers is a test signal, and wherein the corresponding multiplexers receive a data signal as another input.
 7. The apparatus according to claim 5, wherein the corresponding shift registers are coupled together serially, and wherein the apparatus further comprises: test control logic that generates the test pattern, wherein the test control logic is coupled to only a first one of the corresponding shift registers for providing the test pattern to the first one of the corresponding shift registers. 